Amplifying circuit and associated receiver

ABSTRACT

An amplifying circuit includes a first gain adjusting circuit, a second gain adjusting circuit, a load circuit and a switch module. When the amplifying circuit operates in a first mode, the first gain adjusting circuit receives a first input signal, and generates a first output signal to a second output terminal of the amplifying circuit via the load circuit and the switch module; and when the amplifying circuit operates in a second mode, the second gain adjusting circuit receives a second input signal, and generates a second output signal to a first output terminal of the amplifying circuit via the load circuit and the switch module.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to an amplifying circuit, and moreparticularly, to an amplifying circuit comprising a plurality oftransmission paths with a shared loading.

2. Description of the Prior Art

In a conventional amplifying circuit comprising a plurality oftransmission paths, gain adjusting circuits (e.g. an amplifier) on thetransmission paths might output signals with different polarities, i.e.apart of the gain adjusting circuits outputs signals whose polarity issame as the input, and the other part of the gain adjusting circuitsoutputs signals whose polarity is different from the input. Thisdifference in polarity of the input and output might occur when the pathis switched which causes a heavy burden for the following circuits.

On the other hand, when the abovementioned transmission paths share aloading, these paths connect to the same terminal of the loading whichlimits the layout of the circuits.

SUMMARY OF THE INVENTION

One of the objectives of the present invention is therefore to providean amplifying circuit comprising a plurality of transmission paths witha shared path to make sure the polarity of the output signals stays thesame when the path is switched, and make the layout for other circuitsflexible, to solve the aforementioned problems.

According to an embodiment of the present invention, an amplifyingcircuit is disclosed, wherein the amplifying circuit comprises: a firstoutput terminal and a second output terminal; a first gain adjustingcircuit; a second gain adjusting circuit; a loading circuit; and aswitching circuit coupled to the first gain adjusting circuit, thesecond gain adjusting circuit, the loading circuit, the first outputterminal and the second output terminal of the amplifying circuit. Whenthe amplifying circuit operates in a first operating mode, the firstgain adjusting circuit receives a first input signal, and transmits afirst output signal to the second output terminal of the amplifyingcircuit via the switching circuit and the loading circuit, wherein thefirst output signal is not transmitted to the first output terminal atthis point. When the amplifying circuit operates in a second operatingmode, the second gain adjusting circuit receives a second input signal,and transmits a second output signal to the first output terminal viathe switching circuit and the loading circuit, wherein the second outputsignal is not transmitted to the second output terminal at this point.

According to an embodiment of the present invention, a receiver isdisclosed, comprising: a matching circuit; a low noise amplifier; and atransformer. The low noise amplifier comprises: a first output terminaland a second output terminal; a first gain adjusting circuit; a secondgain adjusting circuit; a loading circuit; and a switching circuitcoupled to the first gain adjusting circuit, the second gain adjustingcircuit, the loading circuit, the first output terminal and the secondoutput terminal of the amplifying circuit. When the low noise amplifieroperates in a first operating mode, the first gain adjusting circuitreceives a first input signal from an antenna via the matching circuit,and transmits a first output signal to the second output terminal of thelow noise amplifier via the switching circuit and the loading circuit,wherein the first output signal is not transmitted to the first outputterminal. When the low noise amplifier operates in a second operatingmode, the second gain adjusting circuit receives a second input signalfrom the antenna via the matching circuit, and transmits a second outputsignal to the first output terminal of the low noise amplifier via theswitching circuit and the loading circuit, wherein the second outputsignal is not transmitted to the second output terminal. In addition,one of two terminals of a side coil of the transformer connects to thefirst output terminal of the low noise amplifier, and the other connectsto the second output terminal of the low noise amplifier.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an amplifying circuit according to anembodiment of the present invention.

FIG. 2 is a diagram illustrating two gain adjusting circuits.

FIG. 3 is a diagram illustrating a receiver according to an embodimentof the present invention.

FIG. 4 is a diagram illustrating an amplifying circuit according toanother embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 is a diagram illustrating an amplifying circuit 100 according toan embodiment of the present invention. As shown in FIG. 1, theamplifying circuit 100 comprises gain adjusting circuits 110 and 120, aloading circuit 130, a control signal generating circuit 140 and aswitching circuit, wherein the switching circuit comprises switchesSW1-SW4. In this embodiment, the amplifying circuit 100 comprises twotransmission paths, i.e. the gain adjusting circuits 110 and 120 shownin FIG. 1. In addition, the amplifying circuit 100 is arranged toreceive an input signal Vin for generating an output signal to one ofthe output terminals NF1 and NF2, and the following signal processingcircuits process the output signal according to the voltage differencebetween the output terminal NF1 and NF2.

In this embodiment, the gain adjusting circuits 110 and 120 havedifferent polarity/phase, and can be an amplifier implemented bytransistors, or implemented by passive circuits. In the embodiment ofFIG. 2, the gain adjusting circuit 110 is a capacitor, and the gainadjusting circuit 120 is s source follower, wherein the polarity/phaseof the input and the output of the capacitor are identical, and thepolarity/phase of the input and the output of the source follower aredifferent. It should be noted that FIG. 2 is for illustrative purposes,and not a limitation of the present invention.

In the embodiment of FIG. 1, the loading circuit 130 comprises terminalsN1 and N2, wherein the switch SW1 selectively connects the output signalgenerated by the gain adjusting circuit 110 to the terminal N1 of theloading circuit 130, the switch SW2 selectively connects the terminal N1of the loading circuit 130 to the output terminal NF1 of the amplifyingcircuit 100, the switch SW3 selectively connects the terminal N2 of theloading circuit 130 to the output terminal NF2 of the amplifying circuit100, and the switch SW4 selectively connects the output signal generatedby the gain adjusting circuit 120 to the terminal N2 of the loadingcircuit 130. It should be noted that the composition of the loadingcircuit 130 shown in FIG. 1 is only for illustrative purposes. In otherembodiments, the loading circuit 130 can be a resistor, a capacitor, ora resistor and capacitor connected in parallel.

In this embodiment, the output terminals NF1 and NF2 can selectivelyconnect to any suitable low resistance point and receive a suitabledirect current (DC) voltage, e.g. a supply voltage VDD.

For clarity, the following operation of the amplifying circuit 100 takesthe embodiment of FIG. 2 as example. In the operation of the amplifyingcircuit 100, when the amplifying circuit 100 needs to operate in a firstoperating mode, the control signal generating circuit 140 generatescontrol signals Vc1-Vc4 according to a received mode signal V_mode,wherein the control signals Vc1 and Vc3 are arranged to activate theswitches SW1 and SW3, respectively, and the control signals Vc2 and Vc4are arranged to deactivate the switches SW2 and SW4, respectively. Atthis point, the gain adjusting circuit 110 receives an input signal Vin,and transmits the output signal to the output terminal NF2 via theswitch SW1, the loading circuit 130 and the switch SW3; meanwhile, thegain adjusting circuit 120 does not connect to the loading circuit 130and the output terminals NF1 and NF2 due to the switches SW2 and SW4being deactivated, and the output terminal NF1 does not receive anyoutput signal from the gain adjusting circuits 110 and 120. Moreover, inthis embodiment, the first operating mode is a mode with a low gain or anegative gain.

When the amplifying circuit 100 needs to operate in a second operatingmode, the control signal generating circuit 140 generates the controlsignals Vc1-Vc4 according to the received mode signal V_mode, whereinthe control signals Vc2 and Vc4 are arranged to activate the switchesSW2 and SW4, respectively, and the control signals Vc1 and Vc3 arearranged to deactivate the switches SW1 and SW3, respectively. At thispoint, the gain adjusting circuit 120 receives the input signal Vin, andtransmits the output single to the output terminal NF2 via the switchSW2, the loading circuit 130 and the switch SW4; meanwhile, the gainadjusting circuit 110 does not connect to the loading circuit 130 andthe output terminals NF1 and NF2 due to the switches SW1 and SW3 beingdeactivated, and the output terminal NF1 does not receive any outputsignal from the gain adjusting circuits 110 and 120.

In the abovementioned embodiments, when the amplifying circuit 100operates in the first operating mode, the polarity/phase of the outputsignal generated via the switch SW1, the loading circuit 130 and theswitch SW3 and output to the output terminal NF2 is identical to thepolarity/phase of the input signal because the gain adjusting circuit110 is a capacitor; when the amplifying circuit 100 operates in thesecond operating mode, the polarity/phase of the output signal generatedvia the switch SW4, the loading circuit 130 and the switch SW2 andoutput to the output terminal NF1 is identical to the polarity/phase ofthe input signal because the gain adjusting circuit 120 is a sourcefollower. If the following signal processing circuits process signalsaccording to the voltage difference between the output terminals NF1 andNF2, the signal processing circuits can receive the signals withidentical polarity no matter whether the amplifying circuit 110 operatesin the first operating mode or the second operating mode. The failure ofthe processing signal can therefore be avoided.

Because the gain adjusting circuits 110 and 120 are connected to theterminals N1 and N2 of the loading circuit 130, respectively, the layoutof the circuits can be more flexible which can lower the burden for thedesigner.

In this embodiment, the amplifying circuit 100 can be applied to areceiver. More specifically, refer to FIG. 3 which is a diagramillustrating a receiver 300 according to an embodiment of the presentinvention, wherein the receiver 300 comprises a matching circuit 310, alow noise amplifier 320, a transformer 330 and a signal processingcircuit 340. In the operation of the receiver 300, the matching circuit310 processes the signals from an antenna 302 to generate the inputsignal Vin; the low noise amplifier 320 can be implemented by theamplifying circuit 100 shown in FIG. 1 which is arranged to receive theinput signal Vin and generate output signals to one of the outputterminals NF1 and NF2; the transformers 330 comprise twonon-electrically connected coils, wherein two terminals of a coilconnect to the output terminals NF1 and NF2 of the low noise amplifier320 respectively, and two terminals of the other coil generate voltagesignals to the signal processing circuit 340; the signal processingcircuit 340 processes the received signals. As mentioned above, thepolarity/phase of the signals received by the signal processing circuit340 will not be affected when the operating mode of the low noiseamplifier 320 is switched. The failure of the processing signal canthereby be avoided.

The gain adjusting circuits 110 and 120 of the amplifying circuit 100shown in FIG. 1 receive the same input signal Vin. In other embodiments,however, the gain adjusting circuit 110 and 120 can receive the inputsignal from different sources. FIG. 4 is a diagram illustrating anamplifying circuit 400 according to another embodiment of the presentinvention. As shown in FIG. 4, the amplifying circuit 400 comprises gainadjusting circuits 410 and 420, a loading circuit 430, a control signalgenerating circuit 440 and a switching circuit, wherein the switchingcircuit comprises switches SW1-SW4. In this embodiment, the amplifyingcircuit 400 has two transmission paths, i.e. the gain adjusting circuits410 and 420 shown in FIG. 4.

The operation of the amplifying circuit 400 is similar to the operationof the amplifying circuit 100; the only difference is, when theamplifying circuit 400 operates in the first operating mode, the gainadjusting circuit 410 receives the input signal Vin, and transmits theoutput signal to the output terminal NF2 via the switch SW1, the loadingcircuit 430 and the switch SW3, and the output terminal NF1 does notreceives the output signals from the gain adjusting circuits 410 and420. When the amplifying circuit 400 operates in the second operatingmode, the gain adjusting circuit 420 receives an input signal Vin2, andtransmits the output signal to the output terminal NF1 via the switchSW4, the loading circuit 430 and the switch SW2, and the output terminalNF2 does not receive the output signal from the gain adjusting circuit410 and 420. Those skilled in the art should readily understand theoperation of the amplifying circuit 400 after reading the embodiment ofFIG. 1; the detailed description is therefore omitted here.

Briefly summarized, in the amplifying circuit with two gain adjustingcircuits (i.e. two transmission paths) proposed by the presentinvention, in the case that the polarity of the output signals of thegain adjusting circuits are different, the output signals of the gainadjusting circuits can be transmitted to different output terminals withthe help of the switching circuit to make sure the polarity of theoutput signal of the amplifying circuit will not change in response tothe switch of the gain adjusting circuit, thereby avoiding failure ofthe processing signal. In addition, the gain adjusting circuits areconnected to different terminals of the loading circuit, meaning thelayout of the circuits can be more flexible.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. An amplifying circuit, comprising: a first outputterminal and a second output terminal; a first gain adjusting circuit; asecond gain adjusting circuit; a loading circuit; and a switchingcircuit, coupled to the first gain adjusting circuit, the second gainadjusting circuit, the loading circuit, the first output terminal andthe second output terminal of the amplifying circuit; wherein when theamplifying circuit operates in a first operating mode, the first gainadjusting circuit receives a first input signal, and transmits a firstoutput signal to the second output terminal of the amplifying circuitvia the switching circuit and the loading circuit, and the first outputsignal is not transmitted to the first output terminal at this point;and when the amplifying circuit operates in a second operating mode, thesecond gain adjusting circuit receives a second input signal, andtransmits a second output signal to the first output terminal via theswitching circuit and the loading circuit, and the second output signalis not transmitted to the second output terminal at this point.
 2. Theamplifying circuit of claim 1, wherein a phase of the first outputsignal generated by the first gain adjusting circuit is the same as aphase of the first input signal, and a phase of the second output signalgenerated by the second gain adjusting circuit is the same as a phase ofthe second input signal.
 3. The amplifying circuit of claim 2, whereinthe first gain adjusting circuit is a capacitor, and the second gainadjusting circuit is a source follower.
 4. The amplifying circuit ofclaim 1, wherein when the amplifying circuit operates in the firstoperating mode, the second output signal generated by the second gainadjusting circuit is not received by the first output terminal and thesecond output terminal of the amplifying circuit; and when theamplifying circuit operates in the second operating mode, the firstoutput signal generated by the first gain adjusting circuit is notreceived by the first output terminal and the second output terminal ofthe amplifying circuit.
 5. The amplifying circuit of claim 1, whereinthe loading circuit comprises a first terminal and a second terminal,and the switching circuit comprises: a first switch, arranged toselectively connect the first output signal generated by the first gainadjusting circuit to the first terminal of the loading circuit; a secondswitch, arranged to selectively connect the first terminal of theloading circuit to the first output terminal of the amplifying circuit;a third switch, arranged to selectively connect the second terminal ofthe loading circuit to the second output terminal of the amplifyingcircuit; and a fourth switch, arranged to selectively connect the secondoutput signal generated by the second gain adjusting circuit to thesecond terminal of the loading circuit.
 6. The amplifying circuit ofclaim 5, wherein when the amplifying circuit operates in the firstoperating mode, the first switch and the third switch are activatedwhile the second switch and the fourth switch are deactivated; and whenthe amplifying circuit operates in the second operating mode, the firstswitch and the third switch are deactivated while the second switch andthe fourth switch are activated.
 7. The amplifying circuit of claim 1,wherein one of two terminals of a side coil of a transformer connects tothe first output terminal of the amplifying circuit, and the other ofthe two terminals connects to the second output terminal of theamplifying circuit.
 8. The amplifying circuit of claim 1, wherein theamplifying circuit is a low noise amplifier installed within a receiver.9. A receiver, comprising: a matching circuit; a low noise amplifier,coupled to the matching circuit, comprising: a first output terminal anda second output terminal; a first gain adjusting circuit; a second gainadjusting circuit; a loading circuit; and a switching circuit, coupledto the first gain adjusting circuit, the second gain adjusting circuit,the loading circuit, the first output terminal and the second outputterminal of the low noise amplifier; wherein when the low noiseamplifier operates in a first operating mode, the first gain adjustingcircuit receives a first input signal from an antenna via the matchingcircuit, and transmits a first output signal to the second outputterminal of the low noise amplifier via the switching circuit and theloading circuit, and the first output signal is not transmitted to thefirst output terminal; and when the low noise amplifier operates in asecond operating mode, the second gain adjusting circuit receives asecond input signal from the antenna via the matching circuit, andtransmits a second output signal to the first output terminal of the lownoise amplifier via the switching circuit and the loading circuit, andthe second output signal is not transmitted to the second outputterminal; and a transformer wherein one of two terminals of a side coilof the transformer connects to the first output terminal of the lownoise amplifier, and the other of the two terminals connects to thesecond output terminal of the low noise amplifier.
 10. The receiver ofclaim 9, wherein a phase of the first output signal generated by thefirst gain adjusting circuit is the same as a phase of the first inputsignal, and a phase of the second output signal generated by the secondgain adjusting circuit is the same as a phase of the second inputsignal.